10 · Using IP from Altera's library

Square root, division and a dual-clock FIFO, straight from Altera's library: no wizard, no generated files, no license. Put to work measuring gravity with the on-board accelerometer.

Verified on the board 2026-10-24 Quartus Prime Lite 17.1 No shield needed Skill: use-ip-library

Download ip_library.qar (full project)

The repo keeps the full project (.qar, plus the sources here) but no prebuilt bitstream: one build (a few minutes) makes the .sof on your computer.

Two kinds of IP

Kind	Examples	How to use	License in Lite	Shown in
Megafunctions (built into Quartus)	altpll, altsyncram, dcfifo, scfifo, lpm_divide, altsqrt, lpm_mult, altshift_taps	Instantiate the module directly with parameters	Free	this example, 01, 02
Generated cores	FFT II, FIR II, NCO, CORDIC, floating point	`ip-generate` with parameters, add the `.qip`	Many are evaluation only (time-limited .sof)	11 FFT

What you will see

Where	What
HEX5..HEX0	`G 1.000`: total gravity in g (it stays near 1.000 however you hold the board still)
Your PC	`G=0100 (1000 mg) FLAT%=+076 #05`, 10 lines a second
LEDR9	Accelerometer found (ID E5); LEDR1: FIFO not empty; LEDR0: FIFO full

Measured: G=0100 = 256 counts = 1000 mg exactly; FLAT%=+076: 76 % of gravity points straight down through the board (it leans on its stand); the counter #00, #01, ... proves every word crossed the FIFO in order.

Block diagram

The three megafunctions

altsqrt #(.width(32), .q_port_width(16), .r_port_width(17), .pipeline(4), .lpm_type("altsqrt")) sqrt (
  .radical(sumsq), .clk(clk), .ena(1'b1), .aclr(1'b0), .q(mag), .remainder());

lpm_divide #(.lpm_widthn(24), .lpm_widthd(16), .lpm_nrepresentation("SIGNED"), .lpm_drepresentation("UNSIGNED"),
  .lpm_pipeline(12), .lpm_type("LPM_DIVIDE")) div (
  .numer(z100), .denom(mag), .clock(clk), .clken(1'b1), .aclr(1'b0), .quotient(quot), .remain(rem));

dcfifo #(.lpm_width(32), .lpm_widthu(4), .lpm_numwords(16), .lpm_showahead("OFF"), .lpm_type("dcfifo"),
  .rdsync_delaypipe(4), .wrsync_delaypipe(4), .intended_device_family("MAX 10"), ...) fifo (
  .data(wdata), .wrclk(clk50), .wrreq(wrreq), .wrfull(wrfull), .rdclk(clk25), .rdreq(rdreq), .q(rdata), .rdempty(rdempty), ...);

Where to find the ports and parameters of any megafunction: C:\intelFPGA_lite\17.1\quartus\eda\sim_lib\altera_mf.v (altsqrt, dcfifo, altsyncram ...) and 220model.v (the lpm_* ones). The same files let ModelSim simulate them.

Pipelines: latency for speed

The divider first had 4 pipeline stages and failed timing at 50 MHz by 1.9 ns. With 12 stages it passes: the answer comes 12 clocks later instead of 4, which costs nothing here (a new sample arrives every 10 ms). That trade, more stages for a higher clock, is the knob almost every arithmetic IP gives you. Count the latency and wait for it (the design waits 14 clocks after the square root).

dcfifo vs our byte_cdc

dcfifo is Altera's dual-clock FIFO: any width and depth, in block RAM, with full / empty / used-words flags on both sides. lib/rtl/byte_cdc.sv (example 04) does the same job for bytes in plain Verilog. Use dcfifo when you want wide words or deep buffers.

Run it

python scripts/de10.py build examples/10_ip_library
python scripts/de10.py program examples/10_ip_library
python scripts/de10.py log 3

Build it yourself

python scripts/new_project.py examples/10_ip_library ip_lib_top --lib pll accel print bcd seg7
python scripts/de10.py build examples/10_ip_library

Resources: 2,197 logic elements (4 %), 6 multiplier elements. Timing: no negative slack.

Files

File	What
`src/ip_lib_top.sv`	The example
`lib/rtl/adxl345.sv`, `spi_master.sv`	The accelerometer (example 07)
`lib/rtl/pll_de10.v`	The 25 MHz clock (example 01)